Active matrix display devices

ABSTRACT

An active matrix display device uses an amorphous silicon drive transistor for driving a current through an LED display element. First and second capacitors are connected in series between the gate and source of the drive transistor, with a data input to the pixel provided to the junction between the first and second capacitors. The second capacitor is charged to a pixel data voltage, and a drive transistor threshold voltage is stored on the first capacitor. This pixel arrangement enables a threshold voltage to be stored on the first capacitor, and this can be done each time the pixel is addressed, thereby compensating for age-related changes in the threshold voltage.

This invention relates to active matrix display devices, particularlybut not exclusively active matrix electroluminescent display deviceshaving thin film switching transistors associated with each pixel.

Matrix display devices employing electroluminescent, light-emitting,display elements are well known. The display elements may compriseorganic thin film electroluminescent elements, for example using polymermaterials, or else light emitting diodes (LEDs) using traditional III-Vsemiconductor compounds. Recent developments in organicelectroluminescent materials, particularly polymer materials, havedemonstrated their ability to be used practically for video displaydevices. These materials typically comprise one or more layers of asemiconducting conjugated polymer sandwiched between a pair ofelectrodes, one of which is transparent and the other of which is of amaterial suitable for injecting holes or electrons into the polymerlayer.

The polymer material can be fabricated using a CVD process, or simply bya spin coating technique using a solution of a soluble conjugatedpolymer. Ink-jet printing may also be used. Organic electroluminescentmaterials exhibit diode-like I-V properties, so that they are capable ofproviding both a display function and a switching function, and cantherefore be used in passive type displays. Alternatively, thesematerials may be used for active matrix display devices, with each pixelcomprising a display element and a switching device for controlling thecurrent through the display element.

Display devices of this type have current-driven display elements, sothat a conventional, analogue drive scheme involves supplying acontrollable current to the display element. It is known to provide acurrent source transistor as part of the pixel configuration, with thegate voltage supplied to the current source transistor determining thecurrent through the display element. A storage capacitor holds the gatevoltage after the addressing phase.

FIG. 1 shows a known pixel circuit for an active matrix addressedelectroluminescent display device. The display device comprises a panelhaving a row and column matrix array of regularly-spaced pixels, denotedby the blocks 1 and comprising electroluminescent display elements 2together with associated switching means, located at the intersectionsbetween crossing sets of row (selection) and column (data) addressconductors 4 and 6. Only a few pixels are shown in the Figure forsimplicity. In practice there may be several hundred rows and columns ofpixels. The pixels 1 are addressed via the sets of row and columnaddress conductors by a peripheral drive circuit comprising a row,scanning, driver circuit 8 and a column, data, driver circuit 9connected to the ends of the respective sets of conductors.

The electroluminescent display element 2 comprises an organic lightemitting diode, represented here as a diode element (LED) and comprisinga pair of electrodes between which one or more active layers of organicelectroluminescent material is sandwiched. The display elements of thearray are carried together with the associated active matrix circuitryon one side of an insulating support. Either the cathodes or the anodesof the display elements are formed of transparent conductive material.The support is of transparent material such as glass and the electrodesof the display elements 2 closest to the substrate may consist of atransparent conductive material such as ITO so that light generated bythe electroluminescent layer is transmitted through these electrodes andthe support so as to be visible to a viewer at the other side of thesupport. Typically, the thickness of the organic electroluminescentmaterial layer is between 100 nm and 200 nm. Typical examples ofsuitable organic electroluminescent materials which can be used for theelements 2 are known and described in EP-A-0 717446. Conjugated polymermaterials as described in WO96/36959 can also be used.

FIG. 2 shows in simplified schematic form a known pixel and drivecircuitry arrangement for providing voltage-programmed operation. Eachpixel 1 comprises the EL display element 2 and associated drivercircuitry. The driver circuitry has an address transistor 16 which isturned on by a row address pulse on the row conductor 4. When theaddress transistor 16 is turned on, a voltage on the column conductor 6can pass to the remainder of the pixel. In particular, the addresstransistor 16 supplies the column conductor voltage to a current source20, which comprises a drive transistor 22 and a storage capacitor 24.The column voltage is provided to the gate of the drive transistor 22,and the gate is held at this voltage by the storage capacitor 24 evenafter the row address pulse has ended. The drive transistor 22 draws acurrent from the power supply line 26.

To date, the majority of active matrix circuits for LED displays haveused low temperature polysilicon (LTPS) TFTs. The threshold voltage ofthese devices is stable in time, but varies from pixel to pixel in arandom manner. This leads to unacceptable static noise in the image.Many circuits have been proposed to overcome this problem. In oneexample, each time the pixel is addressed the pixel circuit measures thethreshold voltage of the current-providing TFT to overcome thepixel-to-pixel variations. Circuits of this type are aimed at LTPS TFTsand use p-type devices. Such circuits cannot be fabricated withhydrogenated amorphous silicon (a-Si:H) devices, which is currentlyrestricted to n-type devices.

The use of a-Si:H has however been considered. The variation inthreshold voltage is small in amorphous silicon transistors, at leastover short ranges over the substrate, but the threshold voltage is verysensitive to voltage stress. Application of the high voltages abovethreshold needed for the drive transistor causes large changes inthreshold voltage, which changes are dependent on the informationcontent of the displayed image. There will therefore be a largedifference in the threshold voltage of an amorphous silicon transistorthat is always on compared with one that is not. This differentialageing is a serious problem in LED displays driven with amorphoussilicon transistors.

Generally, proposed circuits using a-Si:H TFTs use current addressingrather than voltage addressing. Indeed, it has also been recognised thata current-programmed pixel can reduce or eliminate the effect oftransistor variations across the substrate. For example, acurrent-programmed pixel can use a current mirror to sample thegate-source voltage on a sampling transistor through which the desiredpixel drive current is driven. The sampled gate-source voltage is usedto address the drive transistor. This partly mitigates the problem ofuniformity of devices, as the sampling transistor and drive transistorare adjacent each other over the substrate and can be more accuratelymatched to each other. Another current sampling circuit uses the sametransistor for the sampling and driving, so that no transistor matchingis required, although additional transistors and address lines arerequired.

The currents required to drive conventional LED devices are quite large,and this has meant that the use of amorphous silicon for active matrixorganic LED displays has been difficult. Recently, OLEDs andsolution-processed OLEDs have shown extremely high efficiencies throughthe use of phosphorescence. Reference is made to the articles‘Electrophosphorescent Organic Light Emitting Devices’, 52.1 SID 02Digest, May 2002, p 1357 by S. R. Forrest et al, and ‘Highly EfficientSolution Processible Dendrimer LEDs’, L-8 SID 02 Digest, May 2002, p1032, by J. P. J. Markham. The required currents for these devices arethen within the reach of a-Si TFTs. However, additional problems comeinto play.

The extremely small currents required for phosphorescent organic LEDsresult in column charging times that are too long for a large display. Afurther problem is the stability (rather than the absolute value) of thethreshold voltage of the TFTs. Under constant bias, the thresholdvoltage of a TFTs increases, therefore simple constant current circuitswill cease to operate after a short time.

Difficulties therefore remain in implementing an addressing schemesuitable for use with pixels having amorphous silicon TFTs, even forphosphorescent LED displays.

According to the invention, there is provided an active matrix devicecomprising an array of display pixels, each pixel comprising:

a current driven light emitting display element;

an amorphous silicon drive transistor for driving a current through thedisplay element;

first and second capacitors connected in series between the gate andsource or drain of the drive transistor, a data input to the pixel beingprovided to the junction between the first and second capacitors therebyto charge the second capacitor to a voltage derived from the pixel datavoltage, and a voltage derived from the drive transistor thresholdvoltage being stored on the first capacitor.

This pixel arrangement enables a threshold voltage to be stored on thefirst capacitor, and this can be done each time the pixel is addressed,thereby compensating for age-related changes in the threshold voltage.Thus, an amorphous silicon circuit is provided that can measure thethreshold voltage of the current-providing TFT once per frame time tocompensate for the aging effect.

In particular, the pixel layout of the invention can overcome thethreshold voltage increase of amorphous silicon TFT, whilst enablingvoltage programming of the pixel in a time that is sufficiently shortfor large high resolution AMOLED displays.

Each pixel may further comprise an input first transistor connectedbetween an input data line and the junction between the first and secondcapacitors. This first transistor times the application of a datavoltage to the pixel, for storage on the second capacitor.

Each pixel may further comprise a second transistor connected betweenthe gate and drain of the drive transistor. This is used to control thesupply of current from the drain (which may be connected to a powersupply line) to the first capacitor. Thus, by turning on the secondtransistor, the first capacitor can be charged to the gate-sourcevoltage. The second transistor may be controlled by a first gate controlline which is shared between a row of pixels.

In one example, the first and second capacitors are connected in seriesbetween the gate and source of the drive transistor. A third transistoris then connected across the terminals of the second capacitor,controlled by a third gate control line which is shared between a row ofpixels. The second and third gate control lines comprise a single sharedcontrol line.

Alternatively, the first and second capacitors can be connected inseries between the gate and drain of the drive transistor. A thirdtransistor is then connected between the input and the source of thedrive transistor. This third transistor can be controlled by a thirdgate control line which is shared between a row of pixels. Again, thesecond and third gate control lines can comprise a single shared controlline.

In each case, the third transistor is used to short out the secondcapacitor so that the first capacitor alone can store the gate-sourcevoltage of the drive transistor.

Each pixel may further comprise a fourth transistor connected betweenthe drive transistor source and a ground potential line. This is used toact as a drain for current from the drive transistor, withoutilluminating the display element, particularly during the pixelprogramming sequence. The fourth transistor can also be controlled by afourth gate control line which is shared between a row of pixels. Theground potential line may be shared between a row of pixels and comprisethe fourth gate control line for the fourth transistors of an adjacentrow of pixels.

In another arrangement, the capacitor arrangement is connected betweenthe gate and source of the drive transistor, and the source of the drivetransistor is connected to a ground line. The drain of the drivetransistor is connected to one terminal of the display element, theother terminal of the display element being connected to a power supplyline. This provides a circuit with reduced complexity, but the circuitelements are on the anode side of the display element.

Each pixel further may further comprise a second transistor connectedbetween the gate and drain of the drive transistor, a shortingtransistor connected across the terminals of the second capacitor, acharging transistor connected between a power supply line and the drainof the drive transistor, and a discharging transistor connected betweenthe gate and drain of the drive transistor.

In some circuits of the invention, the terminal of the display elementopposite to the drive transistor may be connected to a switchablevoltage line. This may be a common cathode line which is shared betweena row of pixels. The ability to change the voltage on this line requiresit to be “structured”, in particular into separate conductors forseparate rows.

In order to avoid the need to provide a structured electrode, and toallow all pixels of the array to share a common display elementelectrode opposite the drive transistor, each pixel may further comprisea second drive transistor. The second drive transistor may be providedbetween a power supply line and the first drive transistor, or elsebetween the first drive transistor and the display element. In eachcase, the second drive transistor provides a way of preventingillumination of the display element during an addressing phase, andwithout needing to change the voltages on a power supply line or on acommon display element terminal.

The display element may comprise an electroluminescent (EL) displayelement, such as an electrophosphorescent organic electroluminescentdisplay element.

The invention also provides a method of driving an active matrix displaydevice comprising an array of current driven light emitting displaypixels, each pixel comprising an display element and an amorphoussilicon drive transistor for driving a current through the displayelement, the method comprising, for each pixel:

driving a current through the drive transistor to ground, and charging afirst capacitor to the resulting gate-source voltage;

discharging the first capacitor until the drive transistor turns off,the first capacitor thereby storing a threshold voltage;

charging a second capacitor, in series with the first capacitor betweenthe gate and source or drain of the drive transistor, to a data inputvoltage; and

using the drive transistor to drive a current through the displayelement using a gate voltage that is derived from the voltages acrossthe first and second capacitors.

This method measures a drive transistor threshold voltage in eachaddressing sequence. The method is for an amorphous silicon TFT pixelcircuit, particularly with an n-type drive TFT, so that a short pixelprogramming must be achieved to enable large displays to be addressed.This can be achieved in this method via threshold voltage measurement ina pipelined addressing sequence (namely with the address sequence foradjacent rows overlapping in time) or by measuring all thresholdvoltages at the beginning of the frame in the blanking period.

In the pipelined address sequence, the step of charging a secondcapacitor is carried out by switching on an address transistor connectedbetween a data line and an input to the pixel. The address transistorfor each pixel in a row is switched on simultaneously by a common rowaddress control line, and the address transistors for one row of pixelsare turned on substantially immediately after the address transistorsfor an adjacent row are turned off.

In the blanking period sequence, the first capacitor of each pixel ischarged to store a respective threshold voltage of the pixel drivetransistor at an initial threshold measurement period of a display frameperiod, a pixel driving period of the frame period following thethreshold measurement period.

The invention will now be described by way of example with reference tothe accompanying drawings, in which:

FIG. 1 shows a known EL display device;

FIG. 2 is a schematic diagram of a known pixel circuit forcurrent-addressing the EL display pixel using an input drive voltage;

FIG. 3 shows a schematic diagram of a first example of pixel layout fora display device of the invention;

FIG. 4 is a timing diagram for a first method of operation of the pixellayout of FIG. 3;

FIG. 5 is a timing diagram for a second method of operation of the pixellayout of FIG. 3;

FIG. 6 is a timing diagram for a third method of operation of the pixellayout of FIG. 3;

FIG. 7 shows a schematic diagram of a second example of pixel layout fora display device of the invention;

FIG. 8 shows example component values for the circuit of FIGS. 3 or 7;

FIG. 9 shows a schematic diagram of a third example of pixel layout withthreshold voltage compensation of the invention;

FIG. 10 is a timing diagram for operation of the pixel layout of FIG. 9;

FIG. 11 shows a schematic diagram of a fourth example of pixel layoutwith threshold voltage compensation of the invention;

FIG. 12 is a timing diagram for operation of the pixel layout of FIG.11.

FIG. 13 shows a schematic diagram of a fifth example of pixel layoutwith threshold voltage compensation of the invention;

FIG. 14 is a timing diagram for a first method of operation of the pixellayout of FIG. 13.

FIG. 15 is a timing diagram for a second method of operation of thepixel layout of FIG. 13.

FIG. 16 is a modification to the timing diagram of FIG. 15;

FIG. 17 shows a schematic diagram of a sixth example of pixel layoutwith threshold voltage compensation of the invention;

FIG. 18 is a timing diagram for a first method of operation of the pixellayout of FIG. 17.

FIG. 19 is a timing diagram for a second method of operation of thepixel layout of FIG. 17; and

FIG. 20 is a modification to the timing diagram of FIG. 18.

The same reference numerals are used in different figures for the samecomponents, and description of these components will not be repeated.

FIG. 3 shows a first pixel arrangement in accordance with the invention.In the preferred embodiments, each pixel has an electroluminescent (EL)display element 2 and an amorphous silicon drive transistor T_(D) inseries between a power supply line 26 and a cathode line 28. The drivetransistor T_(D) is for driving a current through the display element 2.

First and second capacitors C₁ and C₂ are connected in series betweenthe gate and source of the drive transistor T_(D). A data input to thepixel is provided to the junction 30 between the first and secondcapacitors and charges the second capacitor C₂ to a pixel data voltageas will be explained below. The first capacitor C₁ is for storing adrive transistor threshold voltage on the first capacitor C₁.

An input transistor A₁ is connected between an input data line 32 andthe junction 30 between the first and second capacitors. This firsttransistor times the application of a data voltage to the pixel, forstorage on the second capacitor C₂.

A second transistor A₂ is connected between the gate and drain of thedrive transistor T_(D). This is used to control the supply of currentfrom the power supply line 26 to the first capacitor C₁. Thus, byturning on the second transistor A₂, the first capacitor C₁ can becharged to the gate-source voltage of the drive transistor T_(D).

A third transistor A₃ is connected across the terminals of the secondcapacitor C₂. This is used to short out the second capacitor so that thefirst capacitor alone can store the gate-source voltage of the drivetransistor T_(D).

A fourth transistor A₄ is connected between the source of the drivetransistor T_(D) and ground. This is used to act as a drain for currentfrom the drive transistor, without illuminating the display element,particularly during the pixel programming sequence.

The capacitor 24 may comprise an additional storage capacitor (as in thecircuit of FIG. 2) or it may comprise the self-capacitance of thedisplay element.

The transistors A₁ to A₄ are controlled by respective row conductorswhich connect to their gates. As will be explained further below, someof the row conductors may be shared. The addressing of an array ofpixels thus involves addressing rows of pixels in turn, and the dataline 32 comprises a column conductor, so that a full row of pixels isaddressed simultaneously, with rows being addressed in turn, inconventional manner.

The circuit of FIG. 3 can be operated in a number of different ways. Thebasic operation will first be described, and the way this can beextended to provide pipelined addressing is then explained. Pipelinedaddressing means there is some timing overlap between the controlsignals of adjacent rows.

Only the drive transistor T_(D) is used in constant current mode. Allother TFTs A₁ to A₄ in the circuit are used as switches that operate ona short duty cycle. Therefore, the threshold voltage drift in thesedevices is small and does not affect the circuit performance. The timingdiagram is shown in FIG. 4. The plots A₁ to A₄ represent the gatevoltages applied to the respective transistors. Plot “28” represents thevoltage applied to cathode line 28, and the clear part of the plot“DATA” represents the timing of the data signal on the data line 32. Thehatched area represents the time when data is not present on the dataline 32. It will become apparent from the description below that datafor other rows of pixels can be applied during this time so that data isalmost continuously applied to the data line 32, giving a pipelinedoperation.

The circuit operation is to store the threshold voltage of the drivetransistor T_(D) on C_(1,) and then store the data voltage on C₂ so thatthe gate-source of T_(D) is the data voltage plus the threshold voltage.

The circuit operation comprises the following steps.

The cathode (line 28) for the pixels in one row of the display isbrought to a voltage sufficient to keep the LED reversed bias throughoutthe addressing sequence. This is the positive pulse in the plot “28” inFIG. 4.

Address lines A₂ and A₃ go high to turn on the relevant TFTs. Thisshorts out capacitor C₂ and connects one side of capacitor C₁ to thepower line and the other to the LED anode.

Address line A₄ then goes high to turn on its TFT. This brings the anodeof the LED to ground and creates a large gate-source voltage on thedrive TFT T_(D). In this way C₁ is charged, but not C₂ as this remainsshort circuited.

Address line A₄ then goes low to turn off the respective TFT and thedrive TFT T_(D) discharges capacitor C₁ until it reaches its thresholdvoltage. In this way, the threshold voltage of the drive transistorT_(D) is stored on C₁. Again, there is no voltage on the secondcapacitor C₂.

A₂ is brought low to isolate the measured threshold voltage on the firstcapacitor C₁, and A₃ is brought low so that the second capacitor C₂ isno longer short-circuited.

A₄ is then brought high again to connect the anode to ground. The datavoltage is then applied to the second capacitor C₂ whilst the inputtransistor is turned on by the high pulse on A₁.

Finally, A₄ goes low followed by the cathode been brought down toground. The LED anode then floats up to its operating point.

The cathode can alternatively be brought down to ground after A₂ and A₃have been brought low and before A₄ is taken high.

The addressing sequence can be pipelined so that more than one row ofpixels can be programmed at any one time. Thus, the addressing signalson lines A₂ to A₄ and the row wise cathode line 28 can overlap with thesame signals for different rows. Thus, the length of the addressingsequence does not imply long pixel programming times, and the effectiveline time is only limited by the time required to charge the secondcapacitor C₂ when the address line A₁ is high. This time period is thesame as for a standard active matrix addressing sequence. The otherparts of the addressing mean that the overall frame time will only belengthened slightly by the set-up required for the first few rows of thedisplay. However this set can easily be done within the frame-blankingperiod so the time required for the threshold voltage measurement is nota problem.

Pipelined addressing is shown in the timing diagrams of FIG. 5. Thecontrol signals for the transistors A₂ to A₄ have been combined into asingle plot, but the operation is as described with reference to FIG. 4.The “Data” plot in FIG. 5 shows that the data line 32 is used almostcontinuously to provide data to successive rows.

In the method of FIGS. 4 and 5, the threshold measurement operation iscombined with the display operation, so that the threshold measurementand display is performed for each row of pixels in turn.

FIG. 6 shows timing diagrams for a method in which the thresholdvoltages are measured at the beginning of the frame for all pixels inthe display. The plots in FIG. 6 correspond to those in FIG. 4. Theadvantage of this approach is that a structured cathode (namelydifferent cathode lines 28 for different rows, as required to implementthe method of FIGS. 4 and 5) is not required, but the disadvantage isthat leakage currents may result in some image non-uniformity. Thecircuit diagram for this method is still FIG. 3.

As shown in FIG. 6, the signals A₂, A₃, A₄ and the signal for cathodeline 28 in FIG. 6 are supplied to all pixels in the display in ablanking period to perform the threshold voltage measurement. Signal A₄is supplied to every pixel simultaneously in the blanking period, sothat all the signals A₂ to A₄ are supplied to all rows at the same time.During this time, no data can be provided to the pixels, hence theshaded portion of the data plot at the base of FIG. 6.

In the subsequent addressing period, data is supplied separately to eachrow in turn, as is signal A₁. The sequence of pulses on A₁ in FIG. 6represent pulses for consecutive rows, and each pulse is timed with theapplication of data to the data lines 32.

The circuit in FIG. 3 has large number of rows, for the control of thetransistors and for the structure cathode lines (if required). FIG. 7shows a circuit modification which reduces the number of rows required.The timing diagrams show that signals A₂ and A₃ are very similar.Simulations show that A₂ and A₃ can in fact be made the same so thatonly one address line is required. A further reduction can be made byconnecting the ground line associated with the transistor A₄ in FIG. 3to the address line A₄ in a previous row. The circuit in FIG. 7 showsthe address lines for row n and row n-1.

FIG. 8 shows the component values for the circuit of FIG. 3 used in anexample simulation. The length (L) and width (W) dimensions for thetransistors are given in units of μm. The addressing time was 16 μs(i.e. the time A₁ is on). The circuit delivers up to 1.5 μA to the LEDwith 5V above threshold on the drive TFT. TFT mobility was 0.41 cm²/Vs.Using an LED of efficiency 10 Cd/A (currently available Super-yellowPolymer Efficiency) in a pixel of size 400 μm×133 μm will result in 280Cd/m² assuming full aperture in a top-emitting structure.

The simulation shows that a variation of threshold voltage (for thedrive transistor) from 4V up to 10V results in only a 10% change inoutput current. The lifetime of such a display can be calculated to be60,000 hrs at room temperature and 8000 hrs at 40° C.

FIG. 9 shows a modification to the circuit of FIG. 3. Although this willnot be described in detail in this application, the circuit of FIG. 9may be of particular use in a pixel circuit in which each pixel has twoor more drive transistors which are operated alternately. The circuit ofFIG. 9 can be duplicated into a single pixel in a simplified manner, byreducing the component count. This is achieved by allowing some of theTFTs to have dual functions. Where multiple drive transistors areprovided, independent control of either the source or gate of themultiple drive TFTs is required, and all TFTs used for controlling thetwo drive TFTs must operate on a normally off basis i.e. have a low dutycycle, unless these TFTs have some V_(T) drift correction themselves.

The TFT connected to address line A₄ in FIG. 3 will be large, as itneeds to pass the current delivered by the drive TFT in the addressingperiod. Therefore this TFT is an ideal candidate for a dual purpose TFTi.e. one that acts both as a driving TFT and an addressing TFT.Unfortunately the circuit shown in FIG. 3 will not allow this.

In FIG. 9, the same references are used to denote the same components asin the circuit of FIG. 3, and description is not repeated.

In this circuit, the first and second capacitors C₁ and C₂ are connectedin series between the gate and drain of the drive transistor T_(D).Again, the input to the pixel is provided to the junction between thecapacitors. The first capacitor C₁ for storing the threshold voltage isconnected between the drive transistor gate and the input. The secondcapacitor C₂ for storing the data input voltage is connected directlybetween the pixel input and the power supply line (to which thetransistor drain is connected). The transistor connected to control lineA₃, is again for providing a charging path for the first capacitor C₁which bypasses the second capacitor C₂, so that the capacitor C₁ alonecan be used to store a threshold gate-source voltage.

The circuit operation is shown in FIG. 10 and has the following steps:

The cathode for the pixels in one row of the display is brought to avoltage sufficient to keep the LED reversed bias throughout theaddressing sequence.

Address lines A₂ and A₃ go high to turn on the relevant TFTs, thisconnects the parallel combination of C₁ and C₂ to the power line.

Address line A₄ then goes high to turn on its TFT, this brings the anodeof the LED to ground and creates a large gate-source voltage on thedrive TFT T_(D).

Address line A₄ then goes low to turn off the TFT and the drive TFTT_(D) discharges the parallel capacitance C₁+C₂ until it reaches itsthreshold voltage.

Then A₂ and A₃ are brought low to isolate the measured thresholdvoltage.

A₁ is then turned on and the data voltage is stored on capacitance C₁.

Finally A₄ goes low followed by the cathode being brought down toground.

Again, pipelined addressing or threshold measurement in the blankingperiod can be performed with this circuit, as explained above.

A voltage V_(data)−V_(T) is thus stored on the gate-drain of the driveTFT. Therefore:$I = {{\frac{\beta}{2}\left( {V_{gs} - V_{T}} \right)^{2}} = {{\frac{\beta}{2}\left( {V_{ds} - V_{dg} - V_{T}} \right)^{2}} = {\frac{\beta}{2}\left( {V_{ds} - V_{data}} \right)^{2}}}}$

Hence, the threshold voltage dependence is removed. It is noted that thecurrent is now dependent upon the LED anode voltage.

The circuits above have rather a large number of components (due to theindependent gate and source of the driving TFTs). A circuit with onlyone node independent i.e. source or gate can result in a lower componentcount. In the following, a circuit is described that uses circuitry onthe cathode side of the LED and uses independent source voltages toachieve a threshold voltage measurement circuit with recovery. Thethreshold voltage measurement circuit is described with reference toFIG. 11 and the timing diagram is in FIG. 12.

In the circuit of FIG. 11, each pixel has first and second capacitorsC₁, C₂ connected in series between the gate of the drive transistorT_(D) and a ground line. The source of the drive transistor is connectedto the ground line, but when two circuits are combined, the source ofeach drive transistor is then connected to a respective control line. Adata input to the pixel is again provided to the junction between thefirst and second capacitors.

A shorting transistor is connected across the terminals of the secondcapacitor C₂ and controlled by line A₂. As in the previous circuits,this enables a gate-source voltage to be stored on the capacitor C₁bypassing capacitor C₂. A charging transistor associated with controlline A₄ is connected between a power supply line 50 and the drain of thedrive transistor T_(D). This provides a charging path for the capacitorC₁, together with a discharging transistor associated with control lineA₃ and connected between the gate and drain of the drive transistor.

The circuit operates by holding A₂ and A₃ high, A₄ is then held highmomentarily to pull the cathode high and charge the capacitor C₁ to ahigh gate-source voltage. The power line is at ground to reverse biasthe LED. T_(D) then discharges to its threshold voltage (the dischargetransistor associated with line A₁ being turned on) and it is stored onC₁. A₂ and A₃ are then brought low, A₁ is brought high and the data isaddressed onto C₂. The power line is then brought high again to lightthe LED.

Again, the addressing sequence can be pipelined or the thresholdvoltages can be measured in a field blanking period.

In the common-cathode circuits of FIGS. 3, 7 and 9 above, a structuredcathode is required to allow the cathodes of individual rows to beswitched to different voltages during the addressing cycle.

FIG. 13 shows a first modification to the circuit of FIG. 3 to avoid theneed for a structured cathode. A second drive transistor T_(S) isprovided in series with the first drive transistor T_(D), and betweenthe power supply line 26 and the first drive transistor T_(D).

In this circuit, a switchable voltage is provided on the power supplyline 26 (instead of the cathode line 28), and this is used to switch offthe second drive transistor T_(S). The timing of operation is shown inFIG. 14.

As shown, the operation of the circuit is similar to the operation ofthe circuit of FIG. 4. Instead of the cathode 28 being used to switchoff the display element, the power supply line 26 is brought low duringthe addressing sequence. This turns off the second drive transistorT_(S), which is diode-connected with its gate and drain connectedtogether.

The power supply line 26 is high for an initial part of the period whenthe transistors A₂-A₄ are turned on, as the power line is used duringthis time to charge the capacitor C₁ and the second drive transistorT_(S) needs to be on during this time. This initial period issufficiently long for the capacitor C₁ to be charged.

When the power supply line is switched low, the second addresstransistor T_(S) is turned off. As a result, there is no need to switchoff the fourth transistor A₄.

Again, the addressing may be pipelined as shown in FIG. 15, in a similarmanner as explained with reference to FIG. 5.

The addressing scheme of FIG. 15 does not allow any duty cycling of thelight output. This is a technique by which the drive transistors are notilluminated all of the time. This allows the threshold voltage drift tobe reduced, and also allows improved motion portrayal. To provide dutycycle of the drive transistors, the timing operation of FIG. 15 ismodified as shown in FIG. 16.

As explained with reference to FIG. 14, after the capacitor C₁ ischarged, the voltage on the power supply line 26 is brought low to turnoff the current to the display element 2. The first drive transistorT_(D) will still have a gate-source voltage above the threshold, andthis is removed because the transistors A₂ and A₃ so that thesource-drain current of the drive transistor T_(D) removes the charge oncapacitor C₁ until the threshold voltage is reached.

In the scheme of FIG. 16, the power supply line only remains high for afraction (for example half) of the frame period. As shown in FIG. 16,the power supply line 26 is switched low at some point later in theframe period. To ensure that the drive transistor T_(D) is then switchedoff for the remainder of the frame period, a pulse is provided on thecontrol line for transistors A₂ and A₃ as shown, after the power supplyline is switched low.

The fourth transistor A₄ is connected to a ground line in the example ofFIG. 13. However, it is possible for this transistor to be connected tothe power supply line 26 of the previous row (instead of to ground asshown in FIG. 13). The timing of FIG. 16 allows this because when thedrive TFTs from the previous row are having their threshold voltagesmeasured, the power supply line is at ground. This period (labeled 27 inFIG. 16) can be used to act as the ground line for the next row ofpixels during the time when the fourth transistor is turned on. Thus,the address period for A₄ is time to fall within the period when thepower supply line for the previous row is low.

The circuit of FIG. 13 adds a second drive transistor between the powersupply line 26 and the first drive transistor T_(D). This second drivetransistor will pass the same current as the first drive transistorT_(D) and no threshold compensation is therefore required. Thegate-source voltage will float to the required level for the seconddrive transistor to source the current demanded by the first drivetransistor T_(D).

An alternative is to add a second drive transistor between the firstdrive transistor T_(D) and the display element, again to avoid the needto provide a structured cathode. Again, no specific compensation isrequired for the second drive transistor.

An example of such a circuit is shown in FIG. 17. The gate of the seconddrive transistor T_(S) is connected to ground through the fourthtransistor A₄, and a fifth transistor A₅ is connected between the gateand drain of the fifth transistor. Otherwise, the circuit is the same asFIG. 3 and operates in the same way.

As will be apparent from the following, this circuit avoids the need toprovide a switched voltage on either the common cathode terminal of thedisplay elements or on the power supply line.

As shown in FIG. 18, the transistors A₂-A₅ are all switched on at thebeginning of the addressing phase. As for the circuit of FIG. 3, thischarges the capacitor C₁ to a level which causes the drive transistorT_(D) to be turned on, and shorts the capacitor C₂. The source of thedrive transistor T_(D) is connected to ground through the fourth andfifth transistors A₄, A₅. During this time, the second drive transistorT_(S) is turned off, because the gate is coupled to ground through thefourth transistor A₄.

The gate for the fifth transistor A₅ is then brought low to switch itoff. In the same way as for the circuit of FIG. 3, the drive currentthrough the drive transistor (because the source-gate voltage has notchanged) discharges the capacitor C₁ until the threshold voltage isstored. The voltage on the source of the drive transistor is then thepower supply line voltage less the threshold voltage, which is droppedacross C₁.

The transistors A₂ and A₃ are then switched off to isolate thecapacitors. Before the addressing pulse on A₁, the fifth addresstransistor is again turned on. This pulls the source of the drivetransistor T_(D) (and therefore one terminal of the data storagecapacitor C₂) to ground through the fourth and fifth transistors, sothat the data voltage can be stored on C₂ during the addressing phase.

Transistor A₄ is turned off at the end of the addressing pulse in orderto allow the second drive transistor T_(S) to turn on (because its gateis no longer held to ground), and the display element is driven.

Transistor A5 is also turned off at the end of addressing. Thismaintains a short duty cycle for A5 to prevent significant ageing duringoperation. The gate-source and gate-drain parasitic capacitances of A5allow the second drive transistor to remain turned on.

In the same way as explained above, pipelined addressing may be used,and this is shown in FIG. 19.

FIG. 20 shows a modification to the timing sequence explained withreference to FIG. 18. In this case, after the transistors A₂ and A₃ areswitched off to isolate the capacitors, the fifth address transistor isturned on at the same time as the address pulse for A₁. During aninitial part of the addressing pulse, the data line 32 carries a groundvoltage (as shown in the bottom plot). Thus, during an initial part ofthe addressing phase, the junction between the capacitors C₁ and C₂ isalso connected to ground, so that both sides of the capacitor C₂ isgrounded. Thus, no voltage appears across C₂ even though A₃ is turnedoff. This helps to ensure that the threshold voltage of the drivetransistor T_(D) is preserved across C₁ after the data signal is loadedonto C₂.

There are other variations to the specific circuit layouts which canwork in the same way. Essentially, the invention provides a circuitwhich enables a threshold voltage to be stored on one capacitor and adata signal to be stored on another, with these capacitors in seriesbetween the gate and source or drain of the drive transistor. To storethe threshold voltage on the first capacitor, the circuit enables thedrive transistor to be driven using charge from the first capacitor,until the drive transistor turns off, at which point the first capacitorstores a voltage derived from the threshold gate-source voltage.

The circuits can be used for currently available LED devices. However,the electroluminescent (EL) display element may comprise anelectrophosphorescent organic electroluminescent display element. Theinvention enables the use of a-Si:H for active matrix OLED displays.

The circuits above have been shown implemented with only n-typetransistors, and these will all be amorphous silicon devices. Althoughthe fabrication of n-type devices is preferred in amorphous silicon,alternative circuits could of course be implemented with p-type devices.

Various other modifications will be apparent to those skilled in theart.

1. An active matrix device comprising an array of display pixels, eachpixel comprising: a current driven light emitting display element (2);an amorphous silicon drive transistor (T_(D)) for driving a currentthrough the display element; first and second capacitors (C₁, C₂)connected in series between the gate and source or drain of the drivetransistor, a data input to the pixel being provided to the junctionbetween the first and second capacitors (C₁, C₂) thereby to charge thesecond capacitor (C₂) to a voltage derived from the pixel data voltage,and a voltage derived from the drive transistor threshold voltage beingstored on the first capacitor (C₁).
 2. A device as claimed in claim 1,wherein each pixel further comprises an input first transistor (A₁)connected between an input data line (32) and the junction between thefirst and second capacitors (C₁, C₂).
 3. A device as claimed in claim 1,wherein the drain of the drive transistor (T_(D)) is connected to apower supply line (26).
 4. A device as claimed in claim 1, wherein eachpixel further comprises a second transistor (A₂) connected between thegate and drain of the drive transistor
 5. A device as claimed in claim4, wherein the second transistor (A₂) is controlled by a first gatecontrol line which is shared between a row of pixels.
 6. A device asclaimed in claim 1, wherein the first and second capacitors (C₁, C₂) areconnected in series between the gate and source of the drive transistor(T_(D)).
 7. A device as claimed in claim 6, wherein each pixel furthercomprises a third transistor (A₃) connected across the terminals of thesecond capacitor (C₂).
 8. A device as claimed in claim 7, wherein thethird transistor is controlled by a third gate control line which isshared between a row of pixels.
 9. A device as claimed in claim 8,wherein the second and third gate control lines comprise a single sharedcontrol line.
 10. A device as claimed in claim 1, wherein the first andsecond capacitors (C₁, C₂) are connected in series between the gate anddrain of the drive transistor (T_(D)).
 11. A device as claimed in claim10, wherein each pixel further comprises a third transistor (A₃)connected between the input and the source of the drive transistor(T_(D)).
 12. A device as claimed in claim 11, wherein the thirdtransistor (A₃) is controlled by a third gate control line which isshared between a row of pixels.
 13. A device as claimed in claim 12,wherein the second and third gate control lines comprise a single sharedcontrol line.
 14. A device as claimed in claim 1, wherein each pixelfurther comprises a fourth transistor (A₄) connected between the drivetransistor source and a ground potential line.
 15. A device as claimedin claim 14, wherein the fourth transistor (A₄) is controlled by afourth gate control line which is shared between a row of pixels.
 16. Adevice as claimed in claim 15, wherein the ground potential line isshared between a row of pixels and comprises the fourth gate controlline for the fourth transistors of an adjacent row of pixels.
 17. Adevice as claimed in claim 1, wherein the capacitor arrangement (C₁, C₂)is connected between the gate and source of the drive transistor(T_(D)), and the source of the drive transistor is connected to a groundline.
 18. A device as claimed in claim 17, wherein the drain of thedrive transistor (T_(D)) is connected to one terminal of the displayelement (2) the other terminal of the display element being connected toa power supply line.
 19. A device as claimed in claim 17, wherein eachpixel further comprises a second shorting transistor (A₂) connectedacross the terminals of the second capacitor (C₂).
 20. A device asclaimed in claim 17, wherein each pixel further comprises a thirdtransistor (A₃) connected between the gate and drain of the drivetransistor.
 21. A device as claimed in claim 20, wherein the thirdtransistor (A₃) is controlled by a gate control line which is sharedbetween a row of pixels.
 22. A device as claimed in claim 17, whereineach pixel further comprises a fourth charging transistor (A₄) connectedbetween a power supply line (50) and the drain of the drive transistor.23. A device as claimed in claim 1, wherein each pixel further comprisesa second drive transistor (T_(S)).
 24. A device as claimed in claim 23,wherein the second drive transistor is provided between a power supplyline (26) and the first drive transistor (T_(D)).
 25. A device asclaimed in claim 24, wherein the gate and drain of the second drivetransistor are connected together.
 26. A device as claimed in claim 23,wherein the second drive transistor is provided between the first drivetransistor (T_(D)) and the display element (2).
 27. A device as claimedin claim 26, wherein a transistor (A₅) is connected between the gate anddrain of the second drive transistor (T_(S)).
 28. A device as claimed inclaim 26, wherein each pixel further comprises a fourth transistor (A₄)connected between the gate of the second drive transistor (T_(S)) and aground potential line.
 29. A device as claimed in claim 1, wherein thedrive transistor (T_(D)) comprises an n-type transistor.
 30. A device asclaimed in claim 1, wherein the display element comprises anelectroluminescent (EL) display element.
 31. A device as claimed inclaim 30, wherein the electroluminescent (EL) display element comprisesan electrophosphorescent organic electroluminescent display element. 32.A method of driving an active matrix display device comprising an arrayof current driven light emitting display pixels, each pixel comprisingan display element (2) and an amorphous silicon drive transistor (T_(D))for driving a current through the display element, the methodcomprising, for each pixel: driving a current through the drivetransistor (T_(D)) to ground, and charging a first capacitor (C₁) to theresulting gate-source voltage; discharging the first capacitor (C₁)until the drive transistor turns off, the first capacitor therebystoring a threshold voltage; charging a second capacitor (C₂), in serieswith the first capacitor between the gate and source or drain of thedrive transistor, to a data input voltage; and using the drivetransistor (T_(D)) to drive a current through the display element usinga gate voltage that is derived from the voltages across the first andsecond capacitors (C₁, C₂).
 33. A method as claimed in claim 32, whereinthe step of charging a second capacitor is carried out by switching onan address transistor (A₁) connected between a data line and an input tothe pixel.
 34. A method as claimed in claim 33, wherein the addresstransistor for each pixel in a row is switched on simultaneously by acommon row address control line.
 35. A method as claimed in claim 34,wherein the address transistors for one row of pixels are turned onsubstantially immediately after the address transistors for an adjacentrow are turned off.
 36. A method as claimed in claim 32, wherein thefirst capacitor (C₁) of each pixel is charged to store a respectivethreshold voltage of the pixel drive transistor at an initial thresholdmeasurement period of a display frame period, a pixel driving period ofthe frame period following the threshold measurement period.